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6-Channel SMBus or PWM Dimming LED Driver with Phase Shift Control
ISL97673
The ISL97673 is a 6-Channel 45V dual dimming capable LED driver that can be used with either SMBus/I2C or PWM signal for dimming control. The ISL97673 drives 6 channels of LED to support 78 LEDs from 4.5V to 26V or 48 LEDs from a boost supply of 2.7V to 26V and a separate 5V bias on the ISL97673 VIN pin The ISL97673 compensates for non-uniformity of the forward voltage drops in the LED strings with its 6 voltage controlled-current source channels. Its headroom control monitors the highest LED forward voltage string for output regulation, to minimize the voltage headroom and power loss in a typical multi-string operation. The ISL97673 features optional channel phase shift control to minimize the input, output ripple characteristics and load transients as well as spreading the light output to help reduce the video and audio interference from the backlight driver operation. The phase shift can be programmed with equal phase angle or adjustable in 7-bit resolution. The ISL97673 has a full range of dimming capabilities that include SMBus/I2C controlled PWM dimming or DC dimming. Another key feature of the ISL97673 is that it allows very linear PWM dimming from 0.4% to 100% of up to 30kHz. Current matching of 0.4% to 100% dimming achieves 1% tolerance from 100Hz to 5kHz dimming and 3% tolerance from 5kHz to 30kHz dimming.
ISL97673
Features
* 6 Channels * 4.5V to 26.5V Input * 45V Output Max * Up to 40mA LED Current per channel * Extensive Dimming Control - PWM/DPST Dimming, I2C 8-bit with equal phase shift, and 0.007% Direct PWM dimming at 200Hz * Optional Master Fault Protection * PWM Dimming Linearity 0.4%~100% <30kHz * 600kHz/1.2MHz selectable switching frequency * Dynamic Headroom Control * Protections with Flag Indication - String Open/Short Circuit, VOUT Short Circuit, Overvoltage and Over-Temperature Protections - Optional Master Fault Protection * Current Matching 0.7% * 20 Ld 4mmx3mm QFN Package
Applications*(see page 26)
* Notebook Displays WLED or RGB LED Backlighting * LCD Monitor LED Backlighting * Automotive Displays LED Backlighting
Typical Application Circuit
VIN = 4.5~26.5V VOUT = 45V*, 40mA PER CHANNEL
ISL97673
1 FAULT 2 VIN 4 VDC 18 COMP LX 20 OVP 16
PGND 19
7 SMBCLK(SCL)/SEL2 6 SMBDAT(SDA)/ CH0 10 _FLAG CH1 11 3 EN/PWM CH2 12 17 RSET 8 FPWM 5 SEL1 CH3 13 CH4 14 CH5 15 AGND 9
*VIN > 12V
FIGURE 1. ISL97673 TYPICAL APPLICATION DIAGRAM
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL97673
Block Diagram
VIN = 4.5V~26V 10uH/3A VIN VDC REG OSC & RAMP Comp FPWM Dimming Controller
Bias fsw
Fault/Status Register
40mA 45V*, 25mA per string 78 (6x13) LEDs
FAULT O/P Short
LX
4.7uF/50V OVP
OVP
Boost SW
=0
Imax
ILIMIT
Logic
FET Drivers PGND
p e
Fault/Status Control
COMP
GM AMP
Open Ckt, Short Ckt Detects
Highest VF String Detect
VSET
CH0 CH1 CH5
DAC0
DAC0 PWM0 Controls
+ -
0
Temp Sensor
Fault/Status Register
RSET GND
SMBus/ I2C Control
+ -
REF GEN
PWM0
REF_OVP REF_VSC DAC1 PWM1 Controls
DAC1 PWM1
+ -
1
SMBCLK(SCL) SMBDAT(SDA) SEL1 SEL2 EN/PWM
Phase Shift Controller
*VIN > 6V 12V * Vin >
DAC5
D AC5 PWM5 Controls + -
Dimming Mode Selection Ext PWM Control Ckt
5
PWM5
ISL97673
FIGURE 2. ISL97673 BLOCK DIAGRAM
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Ordering Information
PART NUMBER (Notes 1, 2) ISL97673IRZ ISL97673IRZ-EVAL NOTES: 1. Add "-T" or "-TK" suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL97673. For more information on MSL please see techbrief TB363. PART MARKING 7673 PACKAGE (Pb-free) 20 Ld 4x3 QFN PKG. DWG. # L20.3x4
Pin Configuration
ISL97673 (20 LD QFN) TOP VIEW
COMP 18 PGND RSET 17 16 OVP 15 CH5 14 CH4 13 CH3 12 CH2 11 CH1 7 SMBCLK(SCL)/SEL2 8 FPWM 9 AGND 10 CH0 LX 20 FAULT VIN EN/PWM VDC SEL1 1 2 3 4 5 SMBDAT(SDA) 6 /_FLAG
Evaluation Board
19
Pin Descriptions
PIN NAME FAULT VIN EN/PWM
(I = Input, O = Output, S = Supply)
TYPE O S I Fault disconnect switch Input voltage for the device and LED power Dual Functions: Enable pin and PWM brightness control pin or DPST control input. The device needs 4ms for initial power-up Enable, then this pin can be applied with a PWM signal with off time no longer than 28ms. De-couple capacitor for internally generated supply rail. Mode select pin 1 When SEL1 is high, this pin is configured as the SMBus/I2C serial data input/output. When SEL1 is low or floating, this pin is configured as the fault flag output and will be pulled low when a fault condition occurs. An external pull-up is required. When SEL1 is high, this pin is configured as the SMBus/I2C serial clock input. When SEL1 is low or floating, this pins is configured as mode select pin 2, and operates in conjunction with SEL1 to determine the operating mode. See Table 1 for details. PWM Dimming Frequency Set Pin with RFPWM Analog Ground for precision circuits Input 0, Input 1, Input 2, Input 3, Input 4, Input 5 to current source, FB, and monitoring Overvoltage protection input Resistor connection for setting LED current, (see Equation 2 for calculating the ILEDpeak) Boost compensation pin Power ground Input to boost switch DESCRIPTION
PIN NUMBER 1 2 3
VDC SEL1 SMBDAT(SDA)/_FLAG
4 5 6
S I I/O
SMBCLK(SCL)/SEL2
7
I
FPWM AGND CH0, CH1, CH2, CH3, CH4, CH5 OVP RSET COMP PGND LX
8 9 10, 11, 12, 13, 14, 15 16 17 18 19 20
I S I I I O S O
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Table of Contents
Typical Application Circuit ................................. 1 Block Diagram ................................................... 2 Pin Descriptions ................................................ 3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . 5 Thermal Information . . . . . . . . . . . . . . . . . . . . . 5 Operating Conditions . . . . . . . . . . . . . . . . . . . . . 5 Electrical Specifications . . . . . . . . . . . . . . . . . . . 5 Typical Performance Curves .............................. 8 Theory of Operation......................................... 11 PWM Boost Converter ...................................... 11 Enable and PWM ............................................. 11 OVP and VOUT Requirement .............................. 11 Current Matching and Current Accuracy ............. 11 Dynamic Headroom Control .............................. 11 Operating Modes ............................................. 11 Dimming Controls ........................................... 12 Maximum DC Current Setting . . . . . . . . . . . . . . . . . . 12 DC Current Adjustment . . . . . . . . . . . . . . . . . . . . . . . 12 PWM Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PWM Dimming Frequency Adjustment ................ 13 Phase Shift Control . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Switching Frequency........................................14 5V Low Dropout Regulator................................ 14 In-rush Control and Soft-start........................... 14 Fault Protection and Monitoring ......................... 14 Short Circuit Protection (SCP) ........................... 14 Open Circuit Protection (OCP) ........................... 15
Overvoltage Protection (OVP) ........................... 15 Undervoltage Lockout ..................................... 15 Input Overcurrent Protection............................ 15 Over-Temperature Protection (OTP) .................. 15 Write Byte ......................................................... 18 Read Byte ......................................................... 18 Slave Device Address.......................................... 18 SMBus/I2C Register Definitions ........................ 18 PWM Brightness Control Register (0x00)............ 20 Device Control Register (0x01)......................... 20 Fault/Status Register (0x02) ............................ 21 Si Revision Register (0x03) .............................. 21 DC Brightness Control Register (0x07) .............. 22 Configuration Register (0x08) .......................... 22 Output Channel Select and Fault Readout Register (0x09) ............................................ 23 Phase Shift Control Register (0x0A) .................. 24 Components Selections ................................... 24 Input Capacitor .............................................. Inductor ........................................................ Output Capacitors........................................... Output Ripple................................................. Schottky Diode............................................... 24 24 25 25 25
Applications .................................................... 25 High Current Applications ................................ 25 Multiple Drivers Operation ............................... 26 Revision History .............................................. 26 Products.......................................................... 26 Package Outline Drawing ................................ 27
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Absolute Maximum Ratings (TA = +25C)
VIN, EN/PWM. . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 28V FAULT . . . . . . . . . . . . . . . . . . . . . VIN - 8.5V to VIN + 0.3V VDC, COMP, RSET, FPWM, OVP . . . . . . . . . . . . -0.3V to 5.5V SMBCLK(SCL), SMBDAT(SDA) . . . . . . . . . . . . -0.3V to 5.5V CH0 - CH5, LX . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 45V PGND, AGND . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V Above voltage ratings are all with respect to AGND pin ESD Rating Human Body Model (Tested per JESD22-A114E) . . . . . 3kV Machine Model (Tested per JESD22-A115-A) . . . . . . . 300V Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . 1kV
Thermal Information
Thermal Resistance (Typical) 20 Ld QFN Package (Notes 4, 5, 7) . Thermal Characterization (Typical) JA (C/W) JC (C/W) 40 2.5 PSIJT (C/W)
20 Ld QFN Package (Note 6) . . . . . . . . . . . . 1 Maximum Continuous Junction Temperature . . . . . . +125C Storage Temperature . . . . . . . . . . . . . . . -65C to +150C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . -40C to +85C
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 5. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. 6. PSIJT is the PSI junction-to-top thermal characterization parameter. If the package top temperature can be measured with this rating then the die junction temperature can be estimated more accurately than the JC and JC thermal resistance ratings 7. Refer to JESD51-7 high effective thermal conductivity board layout for proper via and plane designs.
Electrical Specifications
All specifications below are tested at TA = +25C; VIN = 12V, EN/PWM = 5V, RSET = 20.1k, unless otherwise noted. Boldface limits apply over the operating temperature range, -40C to +85C. CONDITION MIN (Note 8) TYP MAX (Note 8) UNIT
PARAMETER GENERAL VIN (Note 9) IVIN_STBY VOUT
DESCRIPTION
Backlight Supply Voltage VIN Shutdown Current Output Voltage
11 LEDs per channel (3.2V/20mA type)
4.5
26.5 10
V A V V V V mV
4.5V < VIN 26V, FSW = 600kHz 8.55V < VIN 26V, FSW = 1.2MHz 4.5V < VIN 8.55V, FSW = 1.2MHz
45 45 VIN/0.19 2.6 275 3.3
VUVLO VUVLO_HYS REGULATOR VDC IVDC_STBY IVDC VLDO ENLow ENHi tENLow
Undervoltage Lock-out Threshold Undervoltage Lock-out Hysteresis
LDO Output Voltage Standby Current Active Current VDC LDO Droop Voltage Guaranteed Range for EN Input Low Voltage Guaranteed Range for EN Input High Voltage EN/PWMI Low Time Before Shut-down
VIN > 6V EN/PWMI = 0V EN/PWMI = 5V VIN > 5.5V, 20mA
4.55
4.8
5 5
V A mA
5 20 200 0.5 1.8 30.5
mV V V ms
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Electrical Specifications
All specifications below are tested at TA = +25C; VIN = 12V, EN/PWM = 5V, RSET = 20.1k, unless otherwise noted. Boldface limits apply over the operating temperature range, -40C to +85C. (Continued) CONDITION MIN (Note 8) TYP MAX (Note 8) UNIT
PARAMETER BOOST SWILimit rDS(ON) SS Eff_peak
DESCRIPTION
Boost FET Current Limit Internal Boost Switch ON-resistance Soft-start Peak Efficiency TA = +25C 100% LED Duty Cycle VIN = 12V, 72 LEDs, 20mA each, L = 10H with DCR 101m, TA = +25C VIN = 12V, 60 LEDs, 20mA each, L = 10H with DCR 101m, TA = +25C
1.5
2.0 235 7 92.9
2.7 300
A m ms %
90.8
%
IOUT/VIN DMAX
Line Regulation Boost Maximum Duty Cycle FSW = 1, 600kHz FSW = 0, 1.2MHz 90 81
0.1
% %
DMIN
Boost Minimum Duty Cycle
FSW = 1, 600kHz FSW = 0, 1.2MHz
9.5 17 475 0.97 600 1.14 640 1.31 10
%
fOSC_hi fOSC_lo ILX_leakage
Lx Frequency High Lx Frequency Low Lx Leakage Current
FSW = 1, 600kHz FSW = 0, 1.2MHz LX = 45V, EN = 0
kHz MHz A
FAULT DETECTION VSC Short Circuit Threshold Accuracy Reg0x08, SC[1:0] = 01 Reg0x08, SC[1:0] = 10 Reg0x08, SC[1:0] = 11 Temp_shtdwn Temperature Shutdown Threshold Temp_Hyst VOVPlo OVPfault Temperature Shutdown Hysteresis Overvoltage Limit on OVP Pin OVP Short Detection Fault Level 1.19 400 3.15 4.2 5.2 3.6 4.8 5.85 150 23 1.25 4.3 5.4 6.6 V V V C C V mV
CURRENT SOURCES IMATCH DC Channel-to-Channel Current Matching RSET = 20.1k, Reg0x00 = 0xFF (IOUT = 20mA) -1.5 ILED = 20mA TA = +25C RSET = 20.1k VIN = 12V, VOUT = 45V, Fsw=1.2MHz, TA = +25C 1.2 500 1.22 40 1.24 0.7 1.0 %
IACC Vheadroom VRSET ILEDmax
Current Accuracy Dominant Channel Current Source Headroom at FBx Pin Voltage at RSET Pin Maximum LED Current per Channel
+1.5
% mV mV mA
PWM GENERATOR VIL VIH FPWM PWMACC Guaranteed Range for PWMI Input Low Voltage Guaranteed Range for PWMI Input High Voltage PWMI Input Frequency Range PWM Input Accuracy 1.5 200 8 0.8 VDD 30,000 V V Hz bits
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Electrical Specifications
All specifications below are tested at TA = +25C; VIN = 12V, EN/PWM = 5V, RSET = 20.1k, unless otherwise noted. Boldface limits apply over the operating temperature range, -40C to +85C. (Continued) CONDITION RFPWM = 660k Direct PWM Mode MIN (Note 8) 90 250 TYP 100 MAX (Note 8) 110 350 UNIT Hz ns
PARAMETER FPWM tDIRECTPWM FAULT PIN IFAULT VFAULT LXStart_thres IlxStart-up
DESCRIPTION PWM Dimming Frequency Range Direct PWM Minimum On Time
Fault Pull-down Current Fault Clamp Voltage with Respect to VIN Lx Start-up Threshold Lx Start-up Current
VIN = 12V VIN = 12V, VIN - VFAULT
12 6 1.3 1
21 7 1.4 3.5
30 8.3 1.5 5
A V V mA
SMBus/I2C INTERFACE LOGIC LEVEL VIL VIH VOL ILEAK tEN-SMB/I2C PWS fSMB tBUF tHD:STA tSU:STA tSU:STO tHD:DAT tSU:DAT tLOW tHIGH tF tR NOTES: 8. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 9. Independent from the numbers of LEDs, at minimum VIN of 4.5V, maximum VOUT is limited to 35V. And at maximum VIN of 26.5V, minimum VOUT is limited 28V. 10. Limits established by characterization and are not production tested. Guaranteed Range for Data, Clock Input Low Voltage Guaranteed Range for Data, Clock Input High Voltage SMBus/I2C Output Data Line Logic Low Voltage Input Leakage On SMBData/SMBClk IPULLUP = 4mA Measured at 4.8V -10 1.5 0.8 VDD 0.17 10 V V V A
SMBus/I2C TIMING SPECIFICATIONS (Note 10) Minimum Time Between EN high and SMBus/I2C Enabled Pulse Width Suppression on SMBCLK/SMBDAT SMBus Clock Frequency Bus Free Time Between Stop and Start Condition Hold Time After (Repeated) START Condition. After this Period, the First Clock is Generated Repeated Start Condition Setup Time Stop Condition Setup Time Data Hold Time Data Setup Time Clock Low Period Clock High Period Clock/data Fall Time Clock/data Rise Time 1.3 0.6 0.6 0.6 300 100 1.3 0.6 300 300 1F capacitor on VDC 2 0.15 0.45 400 ms s kHz s s s s ns ns s s ns ns
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Typical Performance Curves
100 90 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0 5 10 15 20 25 EFFICIENCY (%) 80 12VIN 24VIN 5VIN 100 90 80 70 60 50 40 30 20 10 0 0 5 10 15 20 ILED(mA) 25 30 35 12VIN 24VIN 5VIN 6P10S_30mA/CHANNEL
ILED(mA)
FIGURE 3. EFFICIENCY vs up to 20mA LED CURRENT (100% LED DUTY CYCLE) vs VIN
FIGURE 4. EFFICIENCY vs up to 30mA LED CURRENT (100% LED DUTY CYCLE) vs VIN
100 90 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0 5 10 15 VIN 20 25 30 EFFICIENCY (%) 80 580k 1.2MHz
100 80 60 40 20 0 0 580k 1.2MHz
5
10
15 VIN
20
25
30
FIGURE 5. EFFICIENCY vs VIN vs SWITCHING FREQUENCY AT 20mA (100% LED DUTY CYCLE)
100 80 EFFICIENCY (%) 70 +25C 60 50 40 30 20 10 0 0 5 10 15 VIN 20 25 30 +85C 0C -40C
FIGURE 6. EFFICIENCY vs VIN vs SWITCHING FREQUENCY AT 30mA (100% LED DUTY CYCLE)
0.40 CURRENT MATCHING(%) 0.30 0.20 0.10 0.00 -0.10 -0.20 -0.30 -0.40 0 1 2 3 21 VIN 4 5 6 7 4.5 VIN
90
12 VIN
CHANNEL
FIGURE 7. EFFICIENCY vs VIN vs TEMPERATURE AT 20mA (100% LED DUTY CYCLE)
FIGURE 8. CHANNEL-TO-CHANNEL CURRENT MATCHING
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Typical Performance Curves
1.2 1.0 0.8 0.6 0.4 0.2 0
(Continued)
0.60 +25C VHEADROOM (V) 0.55 -40C
CURRENT
4.5 VIN 12 VIN
0.50
0C
0.45
0
1
2
3 DC
4
5
6
0.40 0
5
10
15 VIN (V)
20
25
30
FIGURE 9. CURRENT LINEARITY vs LOW LEVEL PWM DIMMING DUTY CYCLE vs VIN
FIGURE 10. VHEADROOM vs VIN AT 20mA
FIGURE 11. VOUT RIPPLE VOLTAGE, VIN = 12V, 6P12S AT 20mA/CHANNEL
FIGURE 12. IN-RUSH and LED CURRENT AT VIN = 6V FOR 6P12S AT 20mA/CHANNEL
FIGURE 13. IN-RUSH AND LED CURRENT AT VIN = 12V FOR 6P12S AT 20mA/CHANNEL
FIGURE 14. LINE REGULATION WITH VIN CHANGE FROM 6V TO 26V, VIN = 12V, 6P12S AT 20mA/CHANNEL
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Typical Performance Curves
(Continued)
FIGURE 15. LINE REGULATION WITH VIN CHANGE FROM 26V TO 6V FOR 6P12S AT 20mA/CHANNEL
FIGURE 16. LOAD REGULATION WITH ILED CHANGE FROM 0% TO 100% PWM DIMMING, VIN = 12V, 6P12S AT 20mA/CHANNEL
FIGURE 17. LOAD REGULATION WITH ILED CHANGE FROM 100% TO 0% PWM DIMMING, VIN = 12V, 6P12S AT 20mA/CHANNEL
FIGURE 18. ISL97671 SHUTS DOWN AND STOPS SWITCHING ~ 30ms AFTER EN GOES LOW
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Theory of Operation
PWM Boost Converter
The current mode PWM boost converter produces the minimal voltage needed to enable the LED stack with the highest forward voltage drop to run at the programmed current. The ISL97673 employs current mode control boost architecture that has a fast current sense loop and a slow voltage feedback loop. Such architecture achieves a fast transient response that is essential for the notebook backlight application where the power can be a series of drained batteries or instantly change to an AC/DC adapter without rendering a noticeable visual nuisance. The number of LEDs that can be driven by ISL97673 depend on the type of LED chosen in the application. The ISL97673 are capable of boosting up to 45V and typically driving 13 LEDs in series for each of the 6 channels, enabling a total of 104 pieces of the 3.2V/20mA type of LEDs.
The LED peak current is set by translating the RSET current to the output with a scaling factor of 401.8/RSET. The source terminals of the current source MOSFETs are designed to run at 500mV to optimize power loss versus accuracy requirements. The sources of errors of the channel-to-channel current matching come from the op amps offset, internal layout, reference, and current source resistors. These parameters are optimized for current matching and absolute current accuracy. However, the absolute accuracy is additionally determined by the external RSET. A 1% tolerance resistor is recommended.
Enable and PWM
The ISL97673 has EN/PWM pin that serves dual purposes; it is used as an Enable signal and can be used as a PWM input signal for dimming. If a PWM signal is applied to this pin, the first pulse of minimum 4ms will be used as an Enable signal. If there is no signal for longer than 28ms, the device will enter shutdown.
+ RSET + PWM DIMMING DC DIMMING + REF
OVP and VOUT Requirement
The Overvoltage Protection (OVP) pin has a function of setting the overvoltage trip level as well as limiting the VOUT regulation range. The ISL97673 OVP threshold is set by RUPPER and RLOWER as shown in Equation 1:
V OUT_OVP = 1.21V x ( R UPPER + R LOWER ) R LOWER (EQ. 1)
FIGURE 19. SIMPLIFIED CURRENT SOURCE CIRCUIT
Dynamic Headroom Control
The ISL97673 features a proprietary Dynamic Headroom Control circuit that detects the highest forward voltage string or effectively the lowest voltage from any of the CH0-CH5 pins digitally. When the lowest channel voltage is lower than the short circuit threshold, VSC, such voltage will be used as the feedback signal for the boost regulator. The boost makes the output to the correct level such that the lowest channel is at the target headroom voltage. Since all LED stacks are connected to the same output voltage, the other channel pins will have a higher voltage, but the regulated current source circuit on each channel will ensure that each channel has the same current. The output voltage will regulate cycle-bycycle and it is always referenced to the highest forward voltage string in the architecture.
VOUT can only regulate between 64% and 100% of the VOUT_OVP such that: Allowable VOUT = 64% to 100% of VOUT_OVP For example, if 10 LEDs are used with the worst case VOUT of 35V. If R1 and R2 are chosen such that the OVP level is set at 40V, then the VOUT is allowed to operate between 25.6V and 40V. If the requirement is changed to a 6 LEDs 21V VOUT application, then the OVP level must be reduced and users should follow VOUT = (64% ~100%) OVP requirement. Otherwise, the headroom control will be disturbed such that the channel voltage can be much higher than expected and sometimes it can prevent the driver from operating properly. The ratio of the OVP capacitors should be the inverse of the OVP resistors. For example, if RUPPER/RLOWER = 33/1, then CUPPER/CLOWER = 1/33 with CUPPER = 100pF and CLOWER = 3.3nF.
Operating Modes
The ISL97673 has extensive operating modes such as SMBus controlled PWM or DC dimmings, PWM dimming with phase shift control and more. Depending on the pin 5 (SEL1) condition, pins 6 and 7 correspond to different operating modes as shown in Table 1.
Current Matching and Current Accuracy
Each channel of the LED current is regulated by the current source circuit, as shown in Figure 19.
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TABLE 1. SEL1 High Float Float Float Low Low Low SEL2 N/A High Float Low High Float Low OPERATING MODE Selectable by SMBus/I2C Interface PWMI, Fixed-Delay Phase Shift PWM PWMI, Equal-Phase Phase Shift PWM PWMI, No-Delay PWM Not Used DC Current Adjustment Direct PWM
DC CURRENT ADJUSTMENT Once RSET is fixed, the LED DC current can be adjusted through Register 0x07 (BRTDC) as Equation 3:
I LED = 1.58x ( BRTDC R SET ) (EQ. 3)
BRTDC can be programmed from 0 to 255 in decimal and defaults to 255 (0xFF). If left at the default value, LED current will be fixed at ILEDmax. BRTDC can be adjusted dynamically on the fly during operation and a "0" value disconnects all channels. For example, if the maximum required LED current (ILED(max)) is 20mA, rearranging Equation 2 yields Equation 4:
R SET = 401.8 0.02 = 20.1k (EQ. 4)
* When SEL1 is high, Pins 6 and 7 Correspond to SMBDAT and SMBCLK Accordingly. The dimming duty cycle is controlled by the SMBus/I2C communications and the dimming frequency is set by RFPWM. * When SEL1 is floating and SEL2 is high, the channels will be in phase shift mode with fixed delay. The dimming signal is derived from the applied PWMI signal and the dimming frequency is set by RFPWM. * When SEL1 is floating and SEL2 is floating, the channels will be in phase shift mode with equal phase. The dimming signal is derived from the applied PWMI signal and the dimming frequency is set by RFPWM. * When SEL1 is floating and SEL2 is low, the channels phase shift mode is disabled. The dimming signal is derived from the applied PWMI signal and the dimming frequency is set by RFPWM. * When SEL1 is low and SEL2 is high, this combination is not used thus the operation will not change. * When SEL1 is low and SEL2 is floating, it is in DC dimming mode such that the output current is averaged in DC and is proportional to the applied PWMI signal duty cycle. * When SEL1 is low and SEL2 is low, it is in direct PWM mode such that the dimming follows directly from the applied PWMI signal.
If BRTDC is set to 200 then:
I LED = 1.58 * 200 20100 = 15.7mA (EQ. 5)
PWM CONTROL The ISL97673 provides two different PWM dimming methods, as described in the following. Each of these methods results in PWM chopping of the current in the LEDs for all 6 channels to provide an average LED current. During the On periods, the LED current will be defined by the value of RSET and BRTDC, as described in Equations 2 and 3. The source of the PWM signal can be described as follows: 1. SMBus/I2C generated 256 level duty cycle programmed through the SMBus/I2C. 2. External signal from PWM. The default PWM dimming is in SMBus/I2C mode. In both methods, the average LED current of each channel is controlled by ILED and the PWM duty cycle in percent as:
I LED ( ave ) = I LED x PWM (EQ. 6)
Method 1 (SMBus/I2C controlled PWM) To use this mode, users need to set Register 0x01 to 0x05 with EN/PWM in logic high. The average LED current of each channel is controlled by the SMBus/I2C setting as:
I LED ( ave ) = I LED x ( BRT 255 ) (EQ. 7)
Dimming Controls
The ISL97673 allow two ways of controlling the LED current, and therefore, the brightness. They are: 1. DC current adjustment 2. PWM chopping of the LED current defined in Step 1. There are various ways to achieve DC or PWM current control, which will be described in the following. MAXIMUM DC CURRENT SETTING The initial brightness should be set by choosing an appropriate value for RSET. This should be chosen to fix the maximum possible LED current:
( 401.8 ) I LEDmax = ------------------R SET (EQ. 2)
where BRT is the PWM brightness level programmed in the Register 0x00. BRT ranges from 0 to 255 in decimal and defaults to 255 (0xFF). BRT = 0 disconnects all channels.
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Method 2 (External applied PWM) To use this mode users need to set Register 0x01 to 0x03 The average LED current of each channel can also be controlled by an external PWM signal as Equation 8:
I LILED ( ave ) = I LED x PWM (EQ. 8)
PWMI
60% 40%
ILED0 tD1 ILED1
60%
40%
tD1 ILED2 tD1 ILED3 tD1 ILED4 tD1 ILED5 tD2 ILED0 tON tFPWM tOFF
PWM Dimming Frequency Adjustment (Applicable to SMBus/I2C controlled PWM and DPST Modes)
Except for the external PWM dimming mode, the dimming frequencies of any other modes are set by an external resistor at the FPWM pin as Equation 9:
6.66 x10 F PWM = ----------------------RFPWM
7
(EQ. 9) FIGURE 21. 6 EQUAL PHASE CHANNELS PHASE SHIFT ILLUSTRATION
where FPWM is the desirable PWM dimming frequency and RFPWM is the setting resistor. The PWM dimming frequency can be set or applied up to 30kHz with duty cycle from 0.4% to 100%. PHASE SHIFT CONTROL The ISL97673 is capable of delaying the phase of each current source to minimize load transients. By default, phase shifting is disabled as shown in Figure 20 where the channels PWM currents are switching uniformly. The duty cycles can be controlled by the data in PWM Brightness Control Register via the SMBus/I2C interface, an external PWM signal with the frequency set by the RFPWM, or by an external PWM signal with the frequency set by the incoming signal.
tFPWM ILED0 tON tOFF
tPWMin PWMI
60% 40%
tFPWM (tPWMout) ILED1 tD1 ILED2 tD1 ILED3 tD1 ILED4 tON
60%
tOFF
40%
tD2 ILED1
tD1 = Fixed Delay with Integer only while the decimal value will be discarded (eg. 63.75=63)
FIGURE 22. 4 EQUAL PHASE CHANNELS PHASE SHIFT ILLUSTRATION
ILED1
ILED2 ILED3
ILED4
When EqualPhase = 1, the phase shift evenly spreads the channels switching across the PWM cycle, depending on how many channels are enabled, as shown in Figures 21 and 22. Equal phase means there are fixed delays between channels and such delay can be calculated as Equations 10 and 11:
t FPWM 255 t D1 = ------------------ x --------- 255 N t FPWM 255 t D2 = ------------------ x 255 - ( N - 1 ) --------- N 255 (EQ. 10)
ILED5
FIGURE 20. NO DELAY (DEFAULT PHASE SHIFT DISABLED)
(EQ. 11)
where (255/N) is rounded down to the nearest integer. For example, if N = 6, (255/N) = 42, that leads to: tD1 = tFPWM x 42/255 tD2 = tFPWM x 45/255 where tFPWM is the sum of tON and tOFF. N is the number of LED channels. The ISL97673 will detect the numbers of operating channels automatically.
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tFPWM ILED0 tPD ILED1 tPD ILED2 tPD ILED3 tPD ILED4 tPD ILED5 tON tOFF
current in the boost power switch is monitored and the switching is terminated in any cycle where the current exceeds the current limit. The ISL97673 includes a soft-start feature where this current limit starts at a low value (275mA). This is stepped up to the final 2.2A current limit in 7 further steps of 275mA. These steps will happen over at least 8ms, and will be extended at low LED PWM frequencies if the LED duty cycle is low. This allows the output capacitor to be charged to the required value at a low current limit and prevents high input current for systems that have only a low to medium output current requirement. For systems with no master fault protection FET, the inrush current will flow towards COUT when VIN is applied and it is determined by the ramp rate of VIN and the values of COUT and L.
FIGURE 23. PHASE SHIFT WITH 7-BIT PROGRAMMABLE DELAY
The ISL97673 allows the user to program the amount of phase shift degree in 7-bit resolution, as shown in Figure 24. To enable programmable phase shifting, the user must write to the Phase Shift Control register with EqualPhase = 0 and the desirable phase shift value of PhaseShift[6:0]. The delay between CH5 and the repeated CH0 is the rest of the PWM cycle.
Fault Protection and Monitoring
The ISL97673 features extensive protection functions to cover all the perceivable failure conditions. The failure mode of a LED can be either open circuit or as a short. The behavior of an open circuited LED can additionally take the form of either infinite resistance or, for some LEDs, a zener diode, which is integrated into the device in parallel with the now opened LED. For basic LEDs (which do not have built-in zener diodes), an open circuit failure of an LED will only result in the loss of one channel of LEDs without affecting other channels. Similarly, a short circuit condition on a channel that results in that channel being turned off does not affect other channels unless a similar fault is occurring. LED faults are reported via the SMBus/I2C interface to Register 0x02 (Fault/Status register). The controller is able to determine which channels have failed via Register 0x09 (Output Masking register). The controller can also choose to use Register 0x09 to disable faulty channels at start-up, resulting in only further faulty channels being reported by Register 0x02. Due to the lag in boost response to any load change at its output, certain transient events (such as LED current steps or significant step changes in LED duty cycle) can transiently look like LED fault modes. The ISL97673 uses feedback from the LEDs to determine when it is in a stable operating region and prevents apparent faults during these transient events from allowing any of the LED stacks to fault out. See Table 2 for more details. A fault condition that results in high input current due to a short on VOUT will result in a shutdown of all output channels. The control device logic will remain functional such that the Fault/Status Register can be interrogated by the system. The root cause of the failure will be loaded to the volatile Fault/Status Register so that the host processor can interrogate the data for failure monitoring.
Switching Frequency
There are 2 levels of switching frequencies enable for the boost regulator's control of the LX pin: 600kHz or 1.2MHz. Each can be programmed in the Configuration Register 0x08 bit 2. The default switching frequency is at 600kHz.
5V Low Dropout Regulator
A 5V LDO regulator is present at the VDC pin to develop the necessary low voltage supply, which is used by the chips internal control circuitry. Because VDC is an LDO pin, it requires a bypass capacitor of 1F or more for the regulation. Low input voltage also allows only lower output voltage applications only with the maximum boost ratio defined in "Components Selections" on page 24. The VDC pin can be used as a coarse reference with a few mA sourcing capability.
In-rush Control and Soft-start
The ISL97673 has separately built in independent in-rush control and soft-start functions. The in-rush control function is built around the short circuit protection FET, and is only available in applications, which include this device. At start-up, the fault protection FET is turned on slowly due to a 15A pull-down current output from the FAULT pin. This discharges the fault FET's gate-source capacitance, turning on the FET in a controlled fashion. As this happens, the output capacitor is charged slowly through the weakly turned on FET before it becomes fully enhanced. This results in a low in-rush current. This current can be further reduced by adding a capacitor (in the 1nF to 5nF range) across the gate-source terminals of the FET. Once the chip detects that the fault protection FET is turned on hard, it is assumed that in-rush has completed. At this point, the boost regulator will begin to switch and the current in the inductor will ramp-up. The 14
Short Circuit Protection (SCP)
The short circuit detection circuit monitors the voltage on each channel and disables faulty channels which are detected above the programmed short circuit threshold.
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There are three selectable levels of short circuit threshold (3.6V, 4.8V, and 5.85V) that can be programmed through the Configuration Register 0x08. When an LED becomes shorted, the action taken is described in Table 2. The default short circuit threshold is 5.85V. The detection of this failure mode can be disabled via Register 0x08.
Undervoltage Lockout
If the input voltage falls below the UVLO level of 2.45V, the device will stop switching and be reset. Operation will restart only if the device is re-enabled through the SMBus/I2C interface once the input voltage is back in the operating range. In non-SMBus/I2C applications, the part will automatically restart once the input voltage clears the UVLO threshold with the part already enabled.
Open Circuit Protection (OCP)
When one of the LEDs becomes open circuit, it can behave as either an infinite resistance or a gradually increasing finite resistance. The ISL97673 monitors the current in each channel such that any string which reaches the intended output current is considered "good". Should the current subsequently fall below the target, the channel will be considered an "open circuit". Furthermore, should the boost output of the ISL97673 reaches the OVP limit or should the lower over-temperature threshold be reached, all channels which are not "good" will immediately be considered as "open circuit". Detection of an "open circuit" channel will result in a time-out before disabling of the affected channel. This time-out is run when the device is above the lower over-temperature threshold in an attempt to prevent the upper over-temperature trip point from being reached. Some users employ some special types of LEDs that have zener diode structure in parallel with the LED for ESD enhancement, thus enabling open circuit operation. When this type of LED goes open circuit, the effect is as if the LED forward voltage has increased, but no light is emitted. Any affected string will not be disabled, unless the failure results in the boost OVP limit being reached, allowing all other LEDs in the string to remain functional. Care should be taken in this case that the boost OVP limit and SCP limit are set properly, so as to make sure that multiple failures on one string do not cause all other good channels to be faulted out. This is due to the increased forward voltage of the faulty channel making all other channel look as if they have LED shorts. See Table 2 for details for responses to fault conditions.
Input Overcurrent Protection
During normal switching operation, the current through the internal boost power FET is monitored. If the current exceeds the current limit, the internal switch will be turned off. This monitoring happens on a cycle by cycle basis in a self protecting way. Additionally, the ISL97673 monitors the voltage at the LX and OVP pins. At startup, a fixed current is injected out of the LX pins and into the output capacitor. The device will not start up unless the voltage at LX exceeds 1.2V. The OVP pin is also monitored such that if it rises above and subsequently falls below 20% of the target OVP level, the input protection FET will be switched off.
Over-Temperature Protection (OTP)
The ISL97673 includes two over-temperature thresholds. The lower threshold is set to +130C. When this threshold is reached, any channel which is outputting current at a level below the regulation target will be treated as "open circuit" and disabled after a time-out period. The intention of the lower threshold is to allow bad channels to be isolated and disabled before they cause enough power dissipation (as a result of other channels having large voltages across them) to hit the upper temperature threshold. The upper threshold is set to +150C. Each time this is reached, the boost will stop switching and the output current sources will be switched off. Hitting of the upper threshold will also set the thermal fault bit of the Fault/Status register 0x02. Unless disabled via the EN pin, the device stays in an active state throughout, allowing an external processor to interrogate the fault condition. For the extensive fault protection conditions, please refer to Figure 24 and Table 2 for details.
Overvoltage Protection (OVP)
The integrated OVP circuit monitors the output voltage and keeps the voltage at a safe level. The OVP threshold is set as:
OVP = 1.21V x ( R UPPER + R LOWER ) R LOWER (EQ. 12)
These resistors should be large to minimize the power loss. For example, a 1Mk RUPPER and 30k RLOWER sets OVP to 41.2V. Large OVP resistors also allow COUT discharges slowly during the PWM Off time. Parallel capacitors should also be placed across the OVP resistors such that RUPPER/RLOWER = CLOWER/CUPPER. Using a CUPPER value of at least 30pF is recommended. These capacitors reduce the AC impedance of the OVP node, which is important when using high value resistors.
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VIN LX VOUT
DRIVER
FAULT
O/P SHORT
OVP
IMAX
ILIMIT
LOGIC
FET DRIVER
VSC
CH0
VSET/2 REG
CH5
THRM SHDN
REF T2 TEMP SENSOR T1 VSET + Q0 VSET + PWM/OC5/SC5 Q5
OTP
PWM/OC0/SC0 FAULT/ STATUS REGISTER SMB/I2C CONTROL LOGIC
DC CURRENT
FIGURE 24. SIMPLIFIED FAULT PROTECTIONS
TABLE 2. PROTECTIONS TABLE GOOD CHANNELS ACTION CH1 through CH5 Normal VOUT REGULATED BY Highest VF of CH1 through CH5
CASE 1
FAILURE MODE CH0 Short Circuit
DETECTION MODE Upper Over-Temperature Protection limit (OTP) not triggered and CH0 < 4V Upper OTP triggered but VCH0 < 4V
FAILED CHANNEL ACTION CH0 ON and burns power.
2
CH0 Short Circuit
All channels go off until chip cooled and then comes back on with current reduced to 76%. Subsequent OTP triggers will reduce IOUT further. CH1 disabled after 6 PWM cycle time-out. VOUT will ramp to OVP. CH1 will time-out after 6 PWM cycles and switch off. VOUT will drop to normal level. CH1 remains ON and has highest VF, thus VOUT increases.
Same as CH0
Highest VF of CH1 through CH5
3
CH0 Short Circuit
Upper OTP not triggered but CH0 > 4V Upper OTP not triggered and CH0 < 4V Upper OTP not triggered and CH0 < 4V
CH1 through CH5 Normal
Highest VF of CH1 through CH5 Highest VF of CH1 through CH5 VF of CH0
4
CH0 Open Circuit with infinite resistance CH0 LED Open Circuit but has paralleled Zener
CH1 through CH5 Normal
5
CH1 through CH5 ON, Q1 through Q5 burn power
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TABLE 2. PROTECTIONS TABLE (Continued) GOOD CHANNELS ACTION Same as CH0 VOUT REGULATED BY VF of CH0
CASE 6
FAILURE MODE CH0 LED Open Circuit but has paralleled Zener
DETECTION MODE Upper OTP triggered but CH0 < 4V
FAILED CHANNEL ACTION All channels go off until chip cooled and then comes back on with current reduced to 76%. Subsequent OTP triggers will reduce IOUT further CH0 remains ON and has highest VF, thus VOUT increases.
7
CH0 LED Open Circuit but has paralleled Zener
Upper OTP not triggered but CHx > 4V
VOUT increases, then CH-X VF of CH0 switches OFF after 6 PWM cycles. This is an unwanted shut off and can be prevented by setting OVP at an appropriate level. Highest VF of CH0 through CH5 Highest VF of CH0 through CH5 Highest VF of CH0 through CH5
8
Channel-toChannel VF too high Channel-toChannel VF too high Output LED stack voltage too high VOUT/LX shorted to GND at start-up or VOUT shorted in operation
Lower OTP triggered but CHx < 4V Upper OTP triggered but CHx < 4V VOUT > VOVP
Any channel at below the target current will fault out after 6 PWM cycles. Remaining channels driven with normal current. All channels go off until chip cooled and then comes back on with current reduced to 76%. Subsequent OTP triggers will reduce IOUT further Any channel that is below the target current will time-out after 6 PWM cycles, and VOUT will return to the normal regulation voltage required for other channels.
9
10
11
LX current and timing The chip is permanently shutdown 31mS after power-up if VOUT/Lx is shorted to GND. are monitored. OVP pins monitored for excursions below 20% of OVP threshold.
SMBCLK VIH VIL
tLOW
tR
tF
tHD:STA SMBDAT VIH VIL tBUF
tHD:DAT
tHIGH tSU:DAT
tSU:STA
tSU:STO
P
S
S
P
NOTES: SMBus/I2C Description S = start condition P = stop condition A = acknowledge A = not acknowledge R/W = read enable at high; write enable at low
FIGURE 25. SMBus/I2C INTERFACE
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1 S 7 Slave Address Master to Slave Slave to Master 1 W 1 A 8 Command Code 1 A 8 Data byte 1 A 1 P
FIGURE 26. WRITE BYTE PROTOCOL
1 S
7 Slave Address
1 W
1 A
8 Command Code
1 A
1 S
8 Slave Address
1 R
1 A
8 Data Byte
1 A
1 P
Master to Slave Slave to Master
FIGURE 27. READ BYTE PROTOCOL
Write Byte
The Write Byte protocol is only three bytes long. The first byte starts with the slave address followed by the "command code," which translates to the "register index" being written. The third byte contains the data byte that must be written into the register selected by the "command code". A shaded label is used on cycles during which the slaved backlight controller "owns" or "drives" the Data line. All other cycles are driven by the "host master."
mode where bit 0 is 0, the slave address byte is 0x58 or 01011000b. If the device is in the read mode where bit 0 is 1, the slave address byte is 0x59 or 01011001b. The backlight controller may sense the state of the pins at POR or during normal operation. The pins will not change state while the device is in operation.
MSB LSB
Read Byte
As shown in the Figure 27, the four byte long Read Byte protocol starts out with the slave address followed by the "command code" which translates to the "register index." Subsequently, the bus direction turns around with the re-broadcast of the slave address with bit 0 indicating a read ("R") cycle. The fourth byte contains the data being returned by the backlight controller. That byte value in the data byte reflects the value of the register being queried at the "command code" index. Note the bus directions, which are highlighted by the shaded label that is used on cycles during which the slaved backlight controller "owns" or "drives" the Data line. All other cycles are driven by the "host master."
0
1
0
1
1
0
0
R/W
FIGURE 28. SLAVE ADDRESS BYTE DEFINITION
SMBus/I2C Register Definitions
The backlight controller registers are Byte wide and accessible via the SMBus/I2C Read/Write Byte protocols. Their bit assignments are provided in the following sections with reserved bits containing a default value of "0".
Slave Device Address
The slave address contains 7 MSB plus one LSB as R/W bit, but these 8 bits are usually called Slave Address bytes. As shown in Figure 28, the high nibble of the Slave Address byte is 0x5 or 0101b to denote the "backlight controller class." Bit 3 in the lower nibble of the Slave Address byte is 1. Bit 0 is always the R/W bit, as specified by the SMBus/I2C protocol. Note: In this document, the device address will always be expressed as a full 8-bit address instead of the shorter 7-bit address typically used in other backlight controller specifications to avoid confusion. Therefore, if the device is in the write
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DEVICE IDENTIFIER
DEVICE ADDRESS
BI T
ISL97673
TABLE 3A. REGISTER LISTING
ADDRESS 0x00 REGISTER PWM Brightness Control Register BIT 7 BRT7 BIT 6 BRT6 BIT 5 BRT5 BIT 4 BRT4 BIT 3 BRT3 BIT 2 BRT2 BIT 1 BRT1 BIT 0 BRT0 DEFAULT VALUE 0xFF SMBus/I2C PROTOCOL Read and Write
0x01 0x02 0x03 0x07
Device Control Reserved Register Fault/Status Register Si Revision Register DC Brightness Control Register Configuration Register Output Channel Register Phase Shift Deg Reserved 1 BRTDC7
Reserved Reserved 1 BRTDC6
Reserved Reserved Reserved PWM_MD
PWM_SEL
BL_CTL FAULT REV0 BRTDC0
0x00 0x00 0xC8 0xFF
Read and Write Read Only Read Only Read and Write
2_CH_SD 1_CH_SD BL_STAT OV_CURR THRM_SHDN 0 BRTDC5 0 BRTDC4 1 BRTDC3 REV2 BRTDC2 REV1 BRTDC1
0x08 0x09
Reserved DirectPWM PWMtoDC Reserved Reserved CH5
BstSlew Rate1 CH4
BstSlew Rate0 CH3
FSW CH2
VSC1 CH1
VSC0 CH0
0x1F 0x3F
Read and Write Read and Write
0x0A
Equal Phase
Phase Shift6
Phase Shift5
Phase Shift4
Phase Shift3
Phase Shift2
Phase Shift1
Phase Shift0
0x00
Read and Write
TABLE 3B. DATA BIT DESCRIPTIONS ADDRESS 0x00 0x01 REGISTER PWM Brightness Control Register Device Control Register DATA BIT DESCRIPTIONS BRT[7..0] = 256 steps of DPWM duty cycle brightness control PWM_MD = PWM mode select bit (1 = absolute brightness, 0 = % change), default = 0 PWM_SEL = Brightness control select bit (1 = control by PWMI, 0 = control by SMBus/I2C), default = 0 BL_CTL = BL On/Off (1 = On, 0 = Off), default = 0 2_CH_SD = Two LED output channels are shutdown (1 = shutdown, 0 = OK) 1_CH_SD = One LED output channel is shutdown (1 = shutdown, 0 = OK) BL_STAT = BL status (1 = BL On, 0 = BL Off) OV_CURR = Input overcurrent (1 = Overcurrent condition, 0 = Current OK) THRM_SHDN = Thermal Shutdown (1 = Thermal fault, 0 = Thermal OK) FAULT = Fault occurred (Logic "OR" of all of the fault conditions) REV[2..0] = Silicon rev (Rev 0 through Rev 7 allowed for silicon spins) BRTDC[7..0] = 256 steps of DC brightness control DirectPWM = Forces the PWM input signal to directly control the current sources. PWM-to-DC = Switches current sources on and varies DC level rather than PWMing. BstSlewRate = Controls strength of FET driver. 00 - 25% drive strength, 01 - 50% drive strength, 10 - 75% drive strength, 11 - 100% drive strength. FSW = Switching frequencies selection, FSW = 0 = 1.2MHz. FSW = 1 = 600kHz VSC[1..0] = Short circuit thresholds selection, 0 = disabled, 1 = 3.6V, 2 = 4.8V, 3 = 5.8V CH[5..0] = Output Channel Read and Write. In Write, 1 = Channel Enabled, 0 = Channel Disabled. In Read, 1 = Channel OK, 0 = Channel Shutdown or Disabled EqualPhase = Controls phase shift mode - When 0, phase shift is defined by PhaseShift<6:0>. When 1, phase shift is 360/N (where N is the number of channels enabled). PS[6..0] = 7-bit Phase shift setting - phase shift between each channel is PhaseShift<6:0>/(255*PWMFreq). In direct PWM modes, phase shift between each channel is PhaseShift<6:0>/12.8MHz. Note that user must not specify a value that gives >360 shift between first and last channels.
0x02
Fault/Status Register
0x03 0x07 0x08
Si Revision Register DC Brightness Control Register Configuration Register
0x09 0x0A
Output Channel Select and Fault Readout Register Phase Shift Degree
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PWM Brightness Control Register (0x00)
The Brightness control resolution has 256 steps of PWM duty cycle adjustment. The bit assignment is shown in Figure 29. All of the bits in this Brightness Control Register can be read or write. Step 0 corresponds to the minimum step where the current is less than 10A. Steps 1 to 255 represent the linear steps between 0.39% and 100% duty cycle with approximately 0.39% duty cycle adjustment per step. * An SMBus/I2C Write Byte cycle to Register 0x00 sets the PWM brightness level only if the backlight controller is in SMBus/I2C mode (see Table 3A
PWM BRIGHTNESS CONTROL REGISTER BRT5 BRT4 BRT3 BRT2 BRT1 BRT0
Operating Modes selected by Device Control Register Bits 1 and 2). * An SMBus/I2C Read Byte cycle to Register 0x00 returns the programmed PWM brightness level. * An SMBus/I2C setting of 0xFF for Register 0x00 sets the backlight controller to the maximum brightness. * An SMBus/I2C setting of 0x00 for Register 0x00 sets the backlight controller to the minimum brightness output. * Default value for Register 0x00 is 0xFF.
REGISTER 0x00 BRT7 BRT6
Bit 7 (R/W) Bit 6 (R/W) Bit 5 (R/W) Bit 4 (R/W) Bit 3 (R/W) Bit 2 (R/W) Bit 1 (R/W) Bit 0 (R/W) BIT ASSIGNMENT BRT[7..0] BIT FIELD DEFINITIONS = 256 steps of PWM brightness levels FIGURE 29. DESCRIPTIONS OF BRIGHTNESS CONTROL REGISTER
Device Control Register (0x01)
REGISTER 0x01 RESERVED Bit 7 (R/W) DEVICE CONTROL REGISTER PWM_MD PWM_SEL BL_CTL
RESERVED RESERVED RESERVED RESERVED Bit 6 (R/W) Bit 5 (R/W) Bit 4 (R/W) Bit 3 (R/W)
Bit 2 (R/W) Bit 1 (R/W) Bit 0 (R/W)
PWM_MD PWM_SEL X 0 0 1 1 X 0 1 0 1
BL_CTL 0 1 1 1 1 Backlight Off
MODE
SMBus/I2C and PWM dimming (DPST) PWMI controlled PWM dimming SMBus/I2C controlled PWM dimming Backlight On but stays with previous mode selection
FIGURE 30. DESCRIPTIONS OF DEVICE CONTROL REGISTER
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This register has two bits that control either SMBus/I2C controlled or external PWM controlled PWM dimming and a single bit that controls the BL ON/OFF state. The remaining bits are reserved. The bit assignment is shown in Figure 30. All other bits in the Device Control Register will read as low unless otherwise written. * All defined control bits return their current, latched value when read. A value of 1 written to BL_CTL turns on the BL in 4ms or less after the write cycle completes. The BL is * deemed to be on when Bit 3 BL_STAT of Register 0x02 is 1 and Register 0x09 is not 0. * A value of 0 written to BL_CTL immediately turns off the BL. The BL is deemed to be off when Bit 3 BL_STAT of Register 0x02 is 0 and Register 0x09 is 0. * When mode with DPST is selected, Register 0x00 reflects the last value written to it from SMBus/I2C. * The default value for Register 0x01 is 0x00. SMBus/I2C this register are read-only, with the exception of Bit 0, which can be cleared by writing to it. * A Read Byte cycle to Register 0x02 indicates the current BL on/off status in BL_STAT (1 if the BL is on, 0 if the BL is off). * A Read Byte cycles to Register 0x2 also returns FAULT as the logical OR of THRM_SHDN, OV_CURR, 2_CH_SD, and 1_CH_SD should these events occur. * 1_CH_SD returns a 1 if one or more channels have faulted out. * 2_CH_SD returns a 1 if two or more channels have faulted out. * A fault will not be reported in the event that the BL is commanded on and then immediately off by the system. * When FAULT is set to 1, it will remain at 1 even if the signal which sets it goes away. FAULT will be cleared when the BL_CTL bit of the Device Control Register is toggled or when written low. At that time, if the fault condition is still present or reoccurs, FAULT will be set to 1 again. BL_STAT will not cause FAULT to be set. * The default value for Register 0x02 is 0x00.
Fault/Status Register (0x02)
This register has 6 status bits that allow monitoring of the backlight controller's operating state. Bit 0 is a logical "OR" of all fault codes to simplify error detection. Not all of the bits in this register are fault related (Bit 3 is a simple BL status indicator). The remaining bits are reserved and return a "0" when read. All of the bits in
Si Revision Register (0x03)
The Si Revision register has 3 bits that allows up to 8 silicon revisions each. In order to keep the number of silicon revisions low, the revision field will not be updated unless the part will make it out to the user's factory. Thus, if during the first silicon engineering development process, 2 silicon spins were needed, the revision remains as 0. All of the bits in this register are read-only. * The default value for Register 0x03 is 0xC8. The initial value of REV shall be 0. Subsequent values of REV will increment by 1.
REGISTER 0x02
FAULT/STATUS REGISTER 2_CH_SD Bit 5 (R) 1_CH_SD Bit 4 (R) BL_STAT Bit 3 (R) OV_CURR THRM_SHDN Bit 2 (R) Bit 1 (R) FAULT Bit 0 (R)
RESERVED RESERVED Bit 7 (R) BIT Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 6 (R)
BIT ASSIGNMENT 2_CH_SD 1_CH_SD BL_STAT OV_CURR THRM_SHDN FAULT
BIT FIELD DEFINITIONS = Two LED output channels are shutdown (1 = shutdown, 0 = OK) = One LED output channel is shutdown (1 = shutdown, 0 = OK) = BL Status (1 = BL On, 0 = BL Off) = Input Overcurrent (1 = Overcurrent condition, 0 = Current OK) = Thermal Shutdown (1 = Thermal Fault, 0 = Thermal OK) = Fault occurred (Logic "OR" of all of the fault conditions)
FIGURE 31. DESCRIPTIONS OF FAULT/STATUS REGISTER
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REGISTER 0x03 LED PANEL Bit 7 = 1 ID REGISTER
MFG3 Bit 6 (R)
MFG2 Bit 5 (R)
MFG1 Bit 4 (R)
MFG0 Bit 3 (R)
REV2 Bit 2 (R)
REV1 Bit 1 (R)
REV0 Bit 0 (R)
BIT ASSIGNMENT MFG[3..0]
BIT FIELD DEFINITIONS = Manufacturer ID. See "Si Revision Register (0x03)" on page 21. data 0 to 8 in decimal correspond to other vendors data 9 in decimal represents Intersil ID data 10 to 14 in decimal are reserved data 15 in decimal Manufacturer ID is not implemented = Silicon rev (Rev 0 through Rev 7 allowed for silicon spins) FIGURE 32. DESCRIPTIONS OF ID REGISTER
REV[2..0]
DC Brightness Control Register (0x07)
REGISTER 0x07 BRTDC7 BRTDC6 DC BRIGHTNESS CONTROL REGISTER BRTDC5 BRTDC4 BRTDC3 BRTDC2 BRTDC1 BRTDC0
Bit 7 (R/W) Bit 6 (R/W) Bit 5 (R/W) Bit 4 (R/W) Bit 3 (R/W) Bit 2 (R/W) Bit 1 (R/W) Bit 0 (R/W) BIT ASSIGNMENT BRTDC[7..0] BIT FIELD DEFINITIONS = 256 steps of DC brightness levels FIGURE 33. DESCRIPTIONS OF DC BRIGHTNESS CONTROL REGISTER
The DC Brightness Control Register 0x07 allows users to have additional dimming flexibility by: 1. Effectively achieving 16-bits of dimming control when DC dimming is combined with PWM dimming. 2. Achieving visual or audio noise free 8-bit DC dimming over potentially noisy PWM dimming. The bit assignment is shown in Figure 33. All of the bits in this Register can be read or write. Steps 0 to 255 represent the linear steps of current adjustment in DC on the fly. It can also be considered as the peak current factory calibration feature to account for various LED production batch variations, but external EEPROM settings storing and restoring are required. * An SMBus/I2C Write Byte cycle to Register 0x07 sets the brightness level in DC only. * An SMBus/I2C Read Byte cycle to Register 0x07 returns the current DC brightness level. * Default value for Register 0x07 is 0xFF.
Configuration Register (0x08)
The Configuration Register provides many extra functions that users can explore in order to optimize the driver performance at a given application. A Direct PWM bit allows Direct PWM where the output current follows the same input PWM signal. A PWM-to-DC bit allows users to provide convert PWM input into average DC LED current output with the level that is proportional to the input PWM duty cycle. A BstSlewRate bit allows users to control the boost FET slew rate (the rates of turn-on and turn-off). The slew rate can be selected to four relative strengths when driving the internal boost FET. The purpose of this function is to allow users to experiment the slew rate with respect to EMI effect in the system. In general, the slower the slew rate is, the lower the EMI interference to the surrounding circuits; however, the switching loss of the boost FET is also increased. The FSW bit allows users to set the boost conversion switching frequency between 1.2MHz and 600kHz.
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The Vsc bits allow users to set 3 levels of channel short-circuit thresholds or disable it. The bit assignment is shown in Figure 34. The default value for Register 0x08 is 0x1F. of interest. When reading data from this register, any disabled channel and any faulted out channel will read as 0. This allows the user to determine which channel is faulty and optionally not enabling it in order to allow the rest of the system to continue to function. Additionally, a faulted out channel can be disabled and re-enabled in order to allow a retry for any faulty channel without having to power-down the other channels. The bit assignment is shown in Figure 35. The default for Register 0x09 is 0x3F.
Output Channel Select and Fault Readout Register (0x09)
This register can be read or write; the bit position corresponds to the channel. For example, Bit 0 corresponds to CH0 and Bit 4 corresponds to CH4 and so on. Writing data to this register, it enables the channels
REGISTER 0x08 RESERVED Bit 7 (R/W) CONFIGURATION REGISTER PWM-TO-DC Bit 5 (R/W) BSTSLEWRATE1 Bit 4 (R/W)
DIRECT PWM Bit 6 (R/W)
BSTSLEWRATE0 Bit 3 (R/W)
FSW
VSC1
VSC0
Bit 2 (R/W) Bit 1 (R/W) Bit 0 (R/W)
BIT ASSIGNMENT DirectPWM
BIT FIELD DEFINITIONS Forces the PWMI signal to directly control the current sources. Note that there is some synchronous delay between PWMI and current sources. Switches current sources on and varies DC level rather than PWMing. Controls strength of FET driver. 00 - 25% drive strength, 01 to 50% drive strength, 10 -75% drive strength, 11 to 100% drive strength. 2 levels of Switching Frequencies (0 = 1,200kHz, 1 = 600kHz) 3 levels of Short-Circuit Thresholds (0 = disabled, 1 = 3.6V, 2 = 4.8V, 3 = 5.8V) FIGURE 34. DESCRIPTIONS OF CONFIGURATION REGISTER
PWM-to-DC BstSlewRate[1:0] FSW VSC[1..0]
REGISTER 0x09 Reserved Reserved
OUTPUT CHANNEL REGISTER CH5 CH4 CH3 CH2 CH1 CH0
Bit 7 (R/W) Bit 6 (R/W) Bit 5 (R/W) Bit 4 (R/W) Bit 3 (R/W) Bit 2 (R/W) Bit 1 (R/W) Bit 0 (R/W) BIT ASSIGNMENT CH[5..0] BIT FIELD DEFINITIONS CH5 = Channel 5, CH4 = Channel 4 and so on FIGURE 35. DESCRIPTIONS OF OUTPUT CHANNEL REGISTER
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REGISTER 0x0A EQUAL PHASE Bit 7 (R/W) PHASE SHIFT CONTROL REGISTER PHASESHIFT5 Bit 5 (R/W) PHASESHIFT4 Bit 4 (R/W) PHASESHIFT3 Bit 3 (R/W) PHASESHIFT2 Bit 2 (R/W) PHASESHIFT1 Bit 1 (R/W) PHASESHIFT0 Bit 0 (R/W)
PHASESHIFT6 Bit 6 (R/W)
BIT ASSIGNMENT EqualPhase PhaseShift[6..0]
BIT FIELD DEFINITIONS Controls phase shift mode - When 0, phase shift is defined by PhaseShift<6:0>. When 1, phase shift is 360/N (where N is the number of channels enabled). 7-bit Phase shift setting - phase shift between each channel is PhaseShift<6:0>/(255*PWMFreq) In direct PWM modes, phase shift between each channel is PhaseShift<6:0>/12.8MHz Note that user must not specify a value that gives >360 shift between first and last channels. FIGURE 36. DESCRIPTIONS OF PHASE SHIFT CONTROL REGISTER
Phase Shift Control Register (0x0A)
The Phase Shift Control register is used to set phase delay between each channels. When bit 7 is set high, the phase delay is set by the number of channels enabled and the PWM frequency. The delay time is defined by the Equation 13:
t DELAY = ( t FPWM N ) (EQ. 13)
Rearranging the terms without accounting for VD gives the boost ratio and duty cycle respectively as:
VO VI = 1 ( 1 - D ) D = ( VO - VI ) VO (EQ. 17) (EQ. 18)
Input Capacitor
Switching regulators require input capacitors to deliver peak charging current and to reduce the impedance of the input supply. This reduces interaction between the regulator and input supply, thereby improving system stability. The high switching frequency of the loop causes almost all ripple current to flow in the input capacitor, which must be rated accordingly. A capacitor with low internal series resistance should be chosen to minimize heating effects and improve system efficiency, such as X5R or X7R ceramic capacitors, which offer small size and a lower value of temperature and voltage coefficient compared to other ceramic capacitors. In Boost mode, input current flows continuously into the inductor; AC ripple component is only proportional to the rate of the inductor charging, thus, smaller value input capacitors may be used. It is recommended that an input capacitor of at least 10F be used. Ensure the voltage rating of the input capacitor is suitable to handle the full supply range.
where N is the number of channels enabled, and tFPWM is the period of the PWM cycle. When bit 7 is set low, the phase delay is set by bits 6 to 0 and the PWM frequency. The delay time is defined by Equation 14:
t DELAY = ( PS < 6, 0 > xt FPWM ( 255 ) ) (EQ. 14)
where PS is an integer from 0 to 127, and tFPWM is the period of the PWM cycle. By default, all the register bits are set low, which sets zero delay between each channel. Note that the user should not program the register to give more than one period of the PWM cycle delay between the first and last enabled channels.
Components Selections
According to the inductor Voltage-Second Balance principle, the change of inductor current during the switching regulator On time is equal to the change of inductor current during the switching regulator Off time. Since the voltage across an inductor is:
V L = L x I L t (EQ. 15)
Inductor
The selection of the inductor should be based on its maximum current (ISAT) characteristics, power dissipation (DCR), EMI susceptibility (shielded vs unshielded), and size. Inductor type and value influence many key parameters, including ripple current, current limit, efficiency, transient performance and stability. The inductor's maximum current capability must be adequate enough to handle the peak current at the worst case condition. If an inductor core is chosen with too low
FN7633.0 June 24, 2010
and IL @ On = IL @ Off, therefore:
( V I - 0 ) L x D x tS = ( VO - VD - VI ) L x ( 1 - D ) x tS (EQ. 16)
where D is the switching duty cycle defined by the turn-on time over the switching period. VD is Schottky diode forward voltage that can be neglected for approximation.
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a current rating, saturation in the core will cause the effective inductor value to fall, leading to an increase in peak to average current level, poor efficiency and overheating in the core. The series resistance, DCR, within the inductor causes conduction loss and heat dissipation. A shielded inductor is usually more suitable for EMI susceptible applications, such as LED backlighting. The peak current can be derived from the voltage across the inductor during the Off period, as expressed in Equation 19:
IL pk = ( V O x I O ) ( 85% x V I ) + 1 2 [ V I x ( V O - V I ) ( L x V O x f SW ) ] (EQ. 19)
A larger output capacitor will also ease the driver response during PWM dimming Off period due to the longer sample and hold effect of the output drooping. The driver does not need to boost harder in the next On period that minimizes transient current. The output capacitor is also needed for compensation, and, in general one to two 4.7F/50V ceramic capacitors are suitable for netbook to notebook display backlight applications.
Schottky Diode
A high-speed rectifier diode is necessary to prevent excessive voltage overshoot, especially in the boost configuration. Low forward voltage and reverse leakage current will minimize losses, making Schottky diodes the preferred choice. Although the Schottky diode turns on only during the boost switch Off period, it carries the same peak current as the inductor, and therefore, a suitable current rated Schottky diode must be used.
The choice of 85% is just an average term for the efficiency approximation. The first term is the average current, which is inversely proportional to the input voltage. The second term is the inductor current change, which is inversely proportional to L and fSW. As a result, for a given switching frequency and minimum input voltage on which the system operates, the inductor ISAT must be chosen carefully. At a given inductor size, usually the larger the inductance, the higher the series resistance because of the extra winding of the coil. Thus, the higher the inductance, the lower the peak current capability. The ISL97673 current limit should also have to be taken into account.
Applications
High Current Applications
Each channel of the ISL97673 can support up to 30mA. For applications that need higher current, multiple channels can be grouped to achieve the desirable current. For example, the cathode of the last LED can be connected to CH0 to CH2, this configuration can be treated as a single string with 90mA current driving capability.
VOUT
Output Capacitors
The output capacitor acts to smooth the output voltage and supplies load current directly during the conduction phase of the power switch. Output ripple voltage consists of the discharge of the output capacitor for ILPEAK during FET On and the voltage drop due to flowing through the ESR of the output capacitor. The ripple voltage can be shown as Equation 20:
V CO = ( I O C O x D f S ) + ( ( I O x ESR ) (EQ. 20)
CH0 CH1 CH2
The conservation of charge principle in Equation 20 also brings up the fact that during the boost switch Off period, the output capacitor is charged with the inductor ripple current minus a relatively small output current in boost topology. As a result, the user needs to select an output capacitor with low ESR and enough input ripple current capability. The choice of X7R over Y5V ceramic capacitor is highly recommend because X7R capacitor is less sensitive to capacitance change over voltage but the Y5V capacitor exhibits very high capacitance coefficient such that its absolute capacitance can be reduced to 10~20% to the rated capacitance at maximum voltage.
FIGURE 37. GROUPING MULTIPLE CHANNELS FOR HIGH CURRENT APPLICATIONS
SMBCLK SMBDAT EN/PWM
SMBCLK SMBDAT EN/PWM
Output Ripple
VCo, can be reduced by increasing Co or fSW, or using small ESR capacitors. In general, Ceramic capacitors are the best choice for output capacitors in small to medium sized LCD backlight applications due to their cost, form factor, and low ESR.
SMBCLK/SCL SMBDAT/SDA EN
FIGURE 38. MULTIPLE DRIVERS OPERATION
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Multiple Drivers Operation
For large LCD panels where more than 6 channels of LEDs are needed, multiple ISL97673s with each driver having its own supporting components can be controlled together with the common SMBus/I2C. While the ISL97673 does not have extra pins strappable slave address feature, but a separate EN signal can be applied to each driver for asynchronous operation. A trade-off of such scheme is that an exact faulty channel cannot be identified since both ICs have the same I2C slave address.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE 6/24/10 REVISION FN7633.0 Initial Release. CHANGE
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL97673 To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 26
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Package Outline Drawing
L20.3x4
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 3/10
3.00 A B
4
0.10 M C A B 0.05 M C 20X 0.25
+0.05 -0.07
16X 0.50 6 PIN 1 INDEX AREA (C 0.40) 1
A
6 PIN 1 INDEX AREA 16
17
20
4.00 2.65
+0.10 -0.15
11 0.15 (4X) 10 7
+0.10 -0.15
6
A
TOP VIEW
VIEW "A-A"
1.65 20x 0.400.10
BOTTOM VIEW
SEE DETAIL "X"
0.10 C 0.9 0.10
C
SEATING PLANE 0.08 C (16 x 0.50) (2.65) (3.80) (20 x 0.25) C 0.2 REF 5
SIDE VIEW
(20 x 0.60) (1.65) (2.80)
0.00 MIN. 0.05 MAX.
DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature.
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